A typical optical communications network can be topologically broken down into a combination of ring ADM (add-drop multiplexer) systems, linear ADM systems and linear point-to-point systems. While it is possible to define other system categories, it is generally accepted that most optical telecommunications networks consist of one or more of these three classes.
A ring ADM system generally comprises a collection of network elements, each of which is connected to two adjacent network elements by respective segments of optical fiber that usually carries bidirectional traffic according to a standard such as SONET (synchronous optical network) or SDH (synchronous digital hierarchy). Incidentally, while such a ring system is commonly referred to as a ring ADM system, the network elements themselves may be add-drop multiplexers, regenerators, multi-wavelength optical repeaters or switches.
A linear ADM system resembles a broken and unravelled ring ADM system, having a pair of terminal network elements (to each of which only one other network element is connected). A point-to-point linear system, on the other hand, comprises a single pair of network elements joined by optical fiber carrying SONET or SDH traffic.
Network elements are placed at physical locations known as sites. A site generally comprises one or more network elements that belong to various systems (ring ADM, linear ADM, linear point-to-point, etc.), which may or may not communicate information amongst each other. Synchronous operation of the network is achieved through the transmittal of data by the network elements at each site at a precise rate controlled by an electronic clock signal. This clock signal may be generated at the site itself or received from a neighbouring site.
Prior to the advent of SONET, it was common to distribute timing between adjacent sites through the use of a DS1 (digital signal first level) signal. In more recent networks employing SONET, DS1 clock signals are still used for intra-office timing distribution but are derived from incoming optical carrier (OC-N) signals, where N is a multiple of 51.84 Megabits per second and represents the bit rate of the optical signal. A suitable method for deriving DS1 from SONET overhead is described in Bellcore's GR-253 specification, which is hereby incorporated by reference herein.
It is known that the precision of the clock signal used at a site directly influences performance of the network elements at that site when measured in terms of data errors. In general, the higher the precision, the better the performance. In a typical network, the most precise (and expensive) type of clock available is a so-called primary reference source (PRS) clock. The frequency of a PRS clock is usually obtained from an atomic clock or a satellite-based system such as GPS or LORAN-C. A PRS clock is designated as having stratum level 1 (ST1) and its quality is typically measured in terms of its free-run accuracy, as defined in ANSI standard T1.101.
Since PRS clocks are relatively expensive, most sites in the network do not comprise their own PRS clocks. Rather, these "intermediate sites" rely on external timing references from neighbouring upstream sites and also distribute timing to neighbouring downstream sites.
Aside from those intermediate sites which comprise a single network element that terminates a linear ADM system or a chain of linear point-to-point systems, intermediate sites can receive timing signals via at least two potential timing references (PTRs). Derived DS1 synchronization reference signals are extracted from the overhead portion of SONET frames arriving on one of the PTRs known as a "primary" timing reference, which is used under normal circumstances as the preferred timing reference for that site. A second derived DS1 synchronization reference (extracted from another PTR) is used as a "secondary" timing reference in case of failure of the primary timing reference. Since the site typically comprises multiple network elements, timing would ordinarily be distributed to all network elements at the site by means of a building-integrated timing supply (BITS), so that at any given time, a single timing reference provides timing to all the signals leaving the site.
To better explain timing distribution using a BITS, FIG. 1 shows an intermediate site 100 comprising a network element 101 which belongs to a ring system and two network elements 102,103 which join two linear point-to-point systems in a back-to-back configuration. Network element 101 is connected to bidirectional fiber segments 105 and 106, network element 102 is connected to a bidirectional fiber segment 107 and network element 103 is connected to a bidirectional fiber segment 108.
The intermediate site 100 also comprises a BITS 104 for timing distribution, and the site is therefore referred to as an "intermediate BITS site". There are four PTRs provided by the fiber segments 105-108, among which only two are selected as the timing inputs to the BITS 104. Specifically, the SONET frames arriving on fiber segments 105 and 108 are used for the derivation of DS1 timing signals, becoming DS1 timing inputs 115,118 that are fed to the BITS 104. The selection of which two among the four potential timing references arriving on fiber segments 105-108 are to be used for deriving the timing inputs to the BITS 104 is usually effected quite arbitrarily, and the significance of such a selection is often overlooked by network planners.
From its two timing inputs 115,118, the BITS 104 selects, by means of a switch 114, one of these as a timing signal 124 to be distributed to the network elements 101,102,103 at the intermediate BITS site 100. One of the two timing inputs 115,118 is the so-called primary timing reference and under normal conditions is more reliable than the other (secondary) timing reference, e.g., by virtue of being closer to a PRS. Under normal circumstances, therefore, the selected default timing input to be redistributed by the BITS 104 to the network elements 101-103 is the primary timing reference. Under other circumstances, e.g., during fault conditions, the BITS 104 switches over to the secondary timing reference. Assigning one of the timing inputs as the primary timing reference and the other as the secondary timing reference is a system-level decision.
It is also usual to install a BITS at a PRS site, in which case no derivation of DS1 signals from incoming fiber systems is necessary as the highest quality clock is generated at the PRS site itself.
Ensuring a timely switchover from the primary timing reference to the secondary one is an important issue affecting all intermediate sites, regardless of whether or not these sites are BITS-equipped. For example, suppose that a site Y is located between a site X and a site Z, site Y taking its primary clock from site X and its secondary clock from site Z.
If site Y switches from its primary clock to its secondary clock immediately upon detecting degradation of the primary clock (from site X), then the secondary reference (from site Z) is not guaranteed to be reliable. In fact, the clock signal produced by site Z may be a redistribution of a clock signal already distributed to site Z by site Y, in which case site Y would then be relying on an internally generated non-PRS clock. In the network synchronization art, this is known as a timing loop, and has deleterious consequences that include the loss of data.
One straightforward technique which remedies the problem of timing loops is the placement of a PRS clock at every or every second site in the network. While this "solution" is attractive due to its simplicity, it carries with it a hefty price tag for the telecommunications service provider in the form of a multitude (on the order of hundreds) of expensive PRS clocks.
Another way to help reduce the risk of creating timing loops is to use so-called synchronization status messaging (SSM) between neighbouring sites, whereby the quality of a redistributed clock is transmitted to adjacent sites as part of the timing signal itself. Thus, a network element or a BITS equipped with SSM capability reads synchronization-related messages at its two inputs, which control the instant at which the switchover to the secondary timing reference is to be performed. A more complete description of SSM may be found by consulting Bellcore's GR-436-CORE document, revision 1, June 1996, Section 5.4.6, which is hereby incorporated by reference herein.
However, choosing to employ SSM at all the network elements and BITSes in a complex network is expensive and still does not guarantee the elimination of all possible timing loops. In fact, in order to obliterate timing loops entirely, it is necessary to consider the enabling of selected sites with SSM in a joint fashion with the placement of PRS clocks and the installation of BITSes. At the same time, consideration must be given to the cost of installing PRSs and BITSes, and that of enabling sites with SSM. Since the prior art teaches no economical method for jointly considering the above three factors, it is usually the case that network planners apply empirical design methodologies based on years of personal experience with a narrow range of network types, which is a serious disadvantage when the planner is faced with a new, large and entirely different network configuration.